Velocity Saturation in the Extrinsic Device: A Fundamental Limit in HFET’s

We have carried out an experimental study revealing that velocity saturation (usat) occurring in both the extrinsic source and drain sets a fundamental limit on maximum drain current and useful gate swing in HFET’s. Using AlGaAsl n f InCaAs HFET’s as a vehicle, we find that first gm and eventually f~ decline at high currents in two stages. Initially, the approach of vsat in the extrinsic device causes the small-signal source and drain resistances ( T , and ~ d ) to rise dramatically, primarily degrading gm. As the current increases further, the large-signal source and drain resistances (R, and Rd) grow significantly as well, pushing the intrinsic HFET toward the linear regime. Combined with the rapid rise of rS and r d , the accompanying increase in gate-drain capacitance forces f~ to decline through a strongly enhanced Miller effect. We associate this two-fold mechanism with a new regime of HFET operation, which we call the parasitic-resistance blow-up regime.